1. Field of the Invention
The present invention relates to a driver circuit, useful to drive a power switch incorporated in a voltage regulator of the switching type.
More particularly, the invention relates to a driver circuit for driving at least one power switch and comprising a final stage that includes a complementary pair of power transistors connected to a control input of said power switch at a common output node.
2. Description of the Related Art
Voltage regulators of the switching type are widely utilized in many applications on account of their action being effective and accurate. The basic components of a regulator of this type are: one or more power switches, a driver for driving each power switch, passive energy storage elements (capacitors, coils), and a (power management) controller for the control voltage of the driver.
In most of the applications, the power switches are formed of discrete components, such as field-effect power transistors, whereas the controller and the drivers are integrated circuits. The drivers and the controller may either be included in the same integrated circuit or in two separate integrated circuits.
By providing discrete power switches, different technologies can be used and optimized to fill individual demands. For example, the aim of the switches is the one of minimizing switching and conduction losses, whereas the one of the controller and the drivers is the one of using a broad range of integrated components can be used.
It is essential to the overall system efficiency that the power switches be driven in an optimum manner, meaning that in general it should be possible to turn them on/off at a high speed using all the available voltage. This is true in particular for the so-called hard switching systems.
A problem that is often encountered in the design of driver circuits is that supply voltages (VCC) must be used that are optimized for the power switches but not for the components available to make the drivers.
More generally, the problem that must often be addressed is the one of how to produce fast and efficient drivers, which can operate on higher supply voltages than the highest supply voltages accepted by the devices in which they are incorporated.
A typical example of a power switch driver is shown in FIG. 1 of the accompanying drawings. Such driver 1 comprises: a level translator 2 for translation from a first logic voltage, e.g. of 3.3V or 5V, to a power supply voltage VDRV; a pre-driver stage 3 that is referenced to the supply voltage VDRV; and two power switches 4 and 5 operative to respectively close and open an external power switch Mext.
As it is shown in FIG. 2, the power switches 4, 5 may be MOSFET transistors. In particular, the MOSFET transistor for turning on the external switch Mext may be a P-channel transistor M1, and that for turning off the same external switch may be an N-channel transistor M2.
The external switch Mext usually has a high capacitive load, so that to have it turned on and off rapidly, the transistors M1, M2 have to be large ones in order to deliver and/or take in high current peaks. The pre-driver stage, in its turn, should be adequately dimensioned to drive large MOS transistors with high capacitances.
The pre-driver stage 3 is to quickly turn on/off the transistors M1 and M2 in complementary manner to avoid cross-conduction, i.e. prevent M1 and M2 from being simultaneously conductive during the switchings. Also, the stage 3 should keep power consumption down, at the same time as it should limit the control voltages of the switches 4 and 5, as well as of all of its components.
Commercially available regulators mostly use a discrete N-channel MOS transistor as a power switch, since it can easily be driven in a simple manner.
A straightforward solution is provided by the embodiment of FIG. 3, where a driver formed of a succession of inverters 7, 8, 9, of progressively larger size is shown. This structure is known as a xe2x80x9chornxe2x80x9d, and has an advantage in that it is extremely fast and inherently overcomes the cross-conduction problem. Unfortunately, to provide the power MOS transistor with sufficient overdrive to lessen its conduction resistance, the supply voltage to the driver has to be selected above the highest gate-source voltage of the MOS transistors in the inverter.
A prior technical solution allowing the driver to be supplied a higher voltage than the maximum gate-source voltage is illustrated by the schematic of FIG. 4. This prior solution provides separate drives for the transistors M1 and M2, respectively. Here again, the drive should be appropriate to avoid cross-conduction. The drive signal, moreover, is transferred by turning on/off certain current generators 10 and using clamping structures 11 to limit the gate-source voltage of the power transistor. The difficulty lies here in the static draw of the clamping structures 11 and the signal transfer speed being interlinked. For fast turning on and off, the currents from the generators 10 must be large, and these currents are statically absorbed by the clamping structures 11 after the transition.
Turning off the transistors M1, M2 is far more easily effected than turning them on. The gates and sources of the transistors M1 and M2 may be simply short-circuited through an additional MOS transistor 13, that has much smaller dimensions than the ones of the previous M1 and M2. This additional transistor is in its turn driven by a clamping generator 12, but with a much smaller current than that used for turning on the transistors M1 and M2.
To avoid cross-conduction, the power-on and power-off signals may be phase shifted by means of fixed delay blocks 14, 15, as shown in FIG. 5.
A major disadvantage of this prior solution is that the delays must be stretched to prevent malfunction due to process spread and changes in the working conditions.
Shown schematically in FIG. 6 is another prior solution wherein the power-on signals to the transistors M1 and M2 are conditioned logically, each according to the state of the other of the transistors, M2 and M1.
Not even this prior solution can be very effective when the drivers are supplied a low voltage to allow standard logic gates 16 to be used, for otherwise the circuits would become excessively complicated.
An improvement on the last-mentioned solution is disclosed in the European Patent Application No. 99830666.6, in the name of STMicroelectronics S.r.l., wherein a large current is used for turning on/off the transistors M1 and M2. This current is reduced after switching. However, the pre-driver stage 3 is to supply a current throughout the charge/discharge phase of the gate of the external transistor Mext, as well as during the phase of charging/discharging the gates of transistors M1 and M2, due to a parasitic capacitor forming between the gate and the drain of each transistor, M1 and M2.
Thus, the current in this prior solution is not reduced immediately after having charged the gates of the transistors M1, M2, but rather after a predetermined time lapse, taken to be adequate to ensure completion of the transition at the driver output. This is schematically shown in the embodiment of FIG. 7.
The current loop is digitally implemented, i.e. a digital count starts as soon as current is flowed through the clamp of transistor M1, the current being reduced at the end of the count. This solution, therefore, becomes critical wherever the external transistor Mext is a component unknown beforehand, and involves excessive time and power consumption.
A further attempt at solving the driving problems mentioned above is illustrated schematically by the embodiment of FIG. 8. The signal transition is effected by driving a small current generator 17 and a clamp, the latter driving a buffer in the form of an operational amplifier 18, e.g. a compensated two-stage Miller amplifier.
Not even this prior solution is devoid of drawbacks as regards the switching speed of the operational amplifier, which speed is limited by the SR on the Miller compensation capacitor.
Here again, power-off can be readily obtained by means of a small switch toward ground or the supply. Consequently, a buffer used for driving the transistors M1 and M2 into the xe2x80x98onxe2x80x99 state has usually to be asymmetrical, and will be turned on or enabled only during the power-on phases.
An embodiment of this invention provides a novel driver circuit, particularly for a power switch, with appropriate structural and functional features to overcome the aforementioned drawbacks of the prior art.
Briefly, the driver circuit ensures high speed for the power-on and power-off edges, minimizes power consumption, and avoids stressing the gate of the power transistor.
The driver circuit associates, with each power transistor in the complementary pair, a respective power-on buffer stage, each buffer stage being enabled by the xe2x80x98offxe2x80x99 state of its complementary transistor.
This approach allows the transistors of the output stage to be turned on with no limitations on current and with a short delay time.
The features and advantages of a driver circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.